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| lapis semiconducto r fedl9059e-01 issue date: april. 13, 2007 ML9059E 132-channel lcd driver with built-in ram for lcd dot matrix displays 1/72 general description the ML9059E is an lsi for dot matrix graphic lcd devices carrying out bit map display. this lsi can drive a dot matrix graphic lcd display panel under the control of an 8-bit microcomputer (hereinafter described mpu). since all the functions necessary for driving a bit map type lcd device are incorporated in a single chip, using the ML9059E makes it possible to realize a bit map type dot matrix graphic lcd display system with only a few chips. since the bit map method in which one bit of display ram data turns on or off one dot in the display panel, it is possible to carry out displays with a high degree of freedom such as chinese character displays, etc. with one chip, it is possible to construct a graphic display system with a maximum of 49 ? 132 dots. the display can be expanded further using two chips. however, the ML9059E is not used in a multiple chip configuration when a line reversal drive is set. the ML9059E is made using a cmos process. because it has a built-in ram, low power consumption is one of its features, and is therefore suitable for displays in battery-operated portable equipment. the ML9059E has 49 common signal outputs and 132 segment signal outputs and one chip can drive a display of up to 49 ? 132 dots. features ? direct display of the ram data using the bit map method display ram data ?1? ... dot is displayed display ram data ?0? ... dot is not displayed (during forward display) ? display ram capacity 65 ? 132 = 8580 bits ? lcd drive circuits 49 common outputs, 132 segment outputs ? mpu interface: can select an 8-bit parallel or serial interface ? built-in voltage multiplier circuit for the lcd drive power supply ? built-in lcd drive voltage adjustment circuit ? built-in lcd drive bias generator circuit ? can select frame reversal drive or line reversal drive by command ? built-in oscillator circuit (internal rc oscillator/external clock input) ? a variety of commands read/write of display data, display on/off, forwar d/reverse display, all dots on/all dots off, set page address, set display start address, etc. ? power supply voltage logic power supply: v dd -v ss = 3.7 v to 5.5 v voltage multiplier reference voltage: v in -v ss = 3.7 v to 5.5 v (2- to 4-time multiplier available) lcd drive voltage: v bi -v ss = 6.0 to 18 v ? package: gold bump chip (bump hardness: low, dv) : gold bump chip (bump hardness: high, cv) ? this device is not resistant to radiation and light.
fedl9059e-01 lapis semiconductor ML9059E 2/72 block diagram v dd v in frs v1 v2 v3 v4 v5 v ss vs1? vs2? vc3+ vc4+ vc5+ vc6+ v out vr vrs irs segment drivers common drivers common output state selection circuit display data latch circuit display data ram 65 ? 132 column address circuit bus holder c86 c s1 cs2 a 0 r d (e) w r (r/ w ) p/ s r es db7(si) db6(scl) db5 db4 db3 db2 db1 db0 oscillator circuit display timing generator circuit coms coms0 com47 com0 seg131 seg0 line address circuit i/o buffer page address circuit power supply circuit command decoder status mpu lnterface fr cl d o f m/ s cls coms1 test1 fedl9059e-01 lapis semiconductor ML9059E 3/72 absolute maximum ratings v ss = 0 v parameter symbol condition rated value unit applicable pins power supply voltage v dd tj = 25c ?0.3 to +6.5 v v dd bias voltage v bi tj = 25c ?0.3 to +20 v v1 to v5 voltage multiplier output voltage v out tj = 25c ?0.3 to +20 v v out voltage multiplier reference voltage v in 2-time multiplication 3-time multiplication 4-time multiplication ?0.3 to +5.5 ?0.3 to +5.5 ?0.3 to +5.0 v v in input voltage v i tj = 25c ?0.3 to v dd +0.3 v all inputs storage temperature range t stg chip ?55 to +125 c ? tj: chip surface temperature recommended operating conditions v ss = 0 v parameter symbol condition rated value unit applicable pins power supply voltage v dd ? 3.7 to 5.5 v v dd bias voltage v bi ? 6 to 18 v v1 to v5 voltage multiplier reference voltage v in 2-time multiplication 3-time multiplication 4-time multiplication 3.7 to 5.5 3.7 to 5.5 3.7 to 4.5 v v in voltage multiplier output voltage v out external input 6.0 to 18 v v out operating temperature range t jop ? ?40 to +85 c ? note 1: the electrical characteristics are influenced by cog trace resistance. this lsi always has to be evaluated before using. note 2: the voltages v dd , v1 to v5, and v out are values taking v ss = 0 v as the reference. note 3: the highest bias potential is v1 and the lowest is v ss . note 4: always maintain the relationship v1 ? v2 ? v3 ? v4 ? v5 ? v ss among these voltages. v cc gnd v in v dd v ss v out v1 to v5 ML9059E system (mpu) fedl9059e-01 lapis semiconductor ML9059E 4/72 note 5: when using an external power supply, follow the procedure for power application. when applying external power to the v out pin only, apply v out after v dd. when applying external power to the v1 pin only, apply v1 after v dd . when applying external power to the v1 pin to v5 pin, apply v1 to v5 after v dd . note that the above (note 4) must be satisfied including transient state at power application. note 6: when using an external power supply, follow the procedure for power removal described below. when external power is in use for the v out pin only, remove v out after v dd . when external power is in use for the v1 pin only, remove v1 after v dd . when external power is in use for the v1 pin to v5 pin, remove v1 to v5 after v dd . note that the above (note 4) must be satisfied including transient state at power removal. fedl9059e-01 lapis semiconductor ML9059E 5/72 electrical characteristics dc characteristics [v ss = 0 v, v dd = 3.7 to 5.5 v, tj =?40 to +85c] parameter symbol condition min typ max unit applicable pins ?h? input voltage v ih 0.8 ? v dd ? v dd ?l? input voltage v il 0 ? 0.2 ? v dd v *1 ?h? input voltage v ih 0.8 ? v dd ? v dd ?l? input voltage v il 0 ? 0.2 ? v dd hysteresis width ? v v dd = 5.0 v 0.85 1.0 1.55 v *2 ?h? output voltage v oh i oh = ?0.5 ma 0.8 ? v dd ? ? ?l? output voltage v ol i ol = 0.5 ma ? ? 0.2 ? v dd v *3 ?h? input current i ih v i = v dd ?1.0 ? +1.0 ?l? input current i il v i = 0 v ?3.0 ? +3.0 ? a *4 *5 input capacitance c i tj=25c f=10khz ? 8 12 pf *1, *2 v1 output voltage temperature gradient v1tc tj = 25c v1 = 12 v ?0.03 ?0.05 ?0.08 %/c v1 reference voltage v reg tj = 25c 2.925 3.00 3.075 v v rs v1 output voltage v1 *6 10.58 10.85 11.12 v v1 3-time multiplication *7 13.0 ? ? v v out voltage multiplier output voltage v out 4-time multiplication *8 15.9 ? ? v v out v out - v1 voltage vot1 *9 0.6 ? ? v v out, v1 lcd driver on resistance r on i o = ? 50 a ? ? 10 k ? seg1 to 131, coms0, coms1, com0 to 47 27 33 39 khz *10 internal oscillation f osc tj = 25c 21 ? 47 khz oscillator frequency external input f ext 14 17 20 khz cl*10 *1: db0 to db5, db7 (si), fr, dof pins *2: a0, cs1 , cs2, cls, m/ s , c86, p/ s , irs, rd (e), wr (r/ w ), res , cl, db6 (scl) pins *3: db0 to db7, fr, frs, dof , cl pins *4: a0, rd (e), wr (r/w ), cs1 , cs2, cls, m/ s , c86, p/ s , res , irs pins *5: applicable to the pins db0 to db5, db6 (scl), db7 (si), cl, fr, dof in the high impedance state. *6: tj = 25c, ? = 31, (1+rb/ra) = 4, v out = 13.5 v (external input), lcd drive output = no-load *7: v in = 4.8 v, voltage multiplier capacitor c1 = 2.6 to 4.0 ? f, voltage multiplier output load current i = 500 ? a. only a voltage multiplier circuit operates, not activating the voltage adjustment circuit and v/f circuit, by command ?2c?. fedl9059e-01 lapis semiconductor ML9059E 6/72 *8: v in = 4.5 v, voltage multiplier capacitor c1 = 2.6 to 4.0 ? f, voltage multiplier output load current i = 500 ? a. only a voltage multiplier circuit operates, not activating the voltage adjustment circuit and v/f circuit, by command ?2c?. *9: v1 load current i = 400 ? a. 8 v is externally input to v out. the voltage adjustment circuit and v/f circuit operate by command ?2b?. lcd output = no load *10: see table 1 for the relationship between the oscillator frequency and the frame frequency. table 1. relationship among the oscillator frequency (f osc ), external input frequency (f ext ) display clock frequency (f lcdck ), and lcd frame frequency (f fr ) parameter display clock frequency (f lcdck ) lcd frame frequency (f fr ) when the internal oscillator is used f osc /8 f osc /(8 ? 49) ML9059E when the internal oscillator is not used f ext /4 f ext /(4 ? 49) fedl9059e-01 lapis semiconductor ML9059E 7/72 ? o perating current consumption value (1) during display operation, internal power supply off (the current flowing through v dd with v1 to v5 externally applied when an external power supply is used, not including the current for the lcd drive) [v ss = 0 v, tj = 25c] rated value display mode symbol condition min typ max unit v dd = 5 v, v1- v ss = 11 v, no load ? 16 45 all-white i dd v dd = 3.7 v, v1- v ss = 8 v, no load ? 12 35 ? a v dd = 5 v, v1- v ss = 11 v, no load ? 16 45 checker pattern i dd v dd = 3.7 v, v1- v ss = 8 v, no load ? 12 35 ? a (2) during display operation, internal power supply on (total of currents flowing through v dd and v in ) [v ss = 0 v, tj = 25c] rated value display mode symbol condition min typ max unit frame reversal, v dd, v in = 5 v, 3-time voltage multiplication v1 - v ss = 11 v, no load ? 100 170 frame reversal, v dd, v in = 3.7 v, 4-time voltage multiplication v1 - v ss = 8 v, no load ? 110 190 all-white i ddin 16-line reversal, v dd, v in = 5 v, 3-time voltage multiplication v1 - v ss = 11 v, no load ? 100 170 ? a frame reversal, v dd, v in = 5 v, 3-time voltage multiplication v1 - v ss = 11 v, no load ? 120 205 frame reversal, v dd, v in = 3.7 v, 4-time voltage multiplication v1 - v ss = 8 v, no load ? 130 220 checker pattern i ddin 16-line reversal, v dd, v in = 5 v, 3-time voltage multiplication v1 - v ss = 11 v, no load ? 120 205 ? a ? p ower save mode current consumption [v ss = 0 v, tj = 25c] rated value parameter symbol condition min typ max unit sleep mode i dds1 v dd = 3.7 v ? 0.3 5 standby mode i dds2 v dd = 3.7 v ? 9 15 ? a fedl9059e-01 lapis semiconductor ML9059E 8/72 parallel interface timi n g characteristics ? s ystem bus write characteristics 1 (80-series mpu) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? s ystem bus read characteristics 1 (80-series mpu) a0 c s 1 (cs2 = ?h?) wr db0 to db7 (write) t aw8 t ds8 t dh8 t cclw t cchw t ah8 t cyc8 v il v ih v il v ih v ih v il v ih v il v ih v il v ih v il v ih a0 c s 1 (cs2 = ?h?) rd db0 to db7 (read) t aw8 t acc8 t cclr t cchr t ah8 t oh8 t cyc8 v il v ih v il v ih v il v ih v il v ih v ih v oh v oh v ol v ol fedl9059e-01 lapis semiconductor ML9059E 9/72 [v dd = 4.5 to 5.5 v, tj = ?40 to +85c] rated value parameter symbol condition min max unit address hold time t ah8 5 ? address setup time t aw8 5 ? system cycle time t cyc8 166 ? control l pulse width ( wr ) t cclw 30 ? control l pulse width ( rd ) t cclr 70 ? control h pulse width ( wr ) t cchw 55 ? control h pulse width ( rd ) t cchr 55 ? data setup time t ds8 30 ? data hold time t dh8 10 ? rd access time t acc8 ? 70 output disable time t oh8 cl = 100 pf 5 50 ns [v dd = 3.7 to 4.5 v, tj = ?40 to +85c] rated value parameter symbol condition min max unit address hold time t ah8 5 ? address setup time t aw8 5 ? system cycle time t cyc8 300 ? control l pulse width ( wr ) t cclw 60 ? control l pulse width ( rd ) t cclr 120 ? control h pulse width ( wr ) t cchw 60 ? control h pulse width ( rd ) t cchr 60 ? data setup time t ds8 40 ? data hold time t dh8 15 ? rd access time t acc8 ? 140 output disable time t oh8 cl = 100 pf 10 100 ns note 1: the input signal rise and fall times are specified as 15ns or less. when using the system cycle time for fast speed, the specified values are (tr + tf) ? (t cyc8 ? t cclw ? t cchw ) or (tr + tf) ? (t cyc8 ? t cclr ? t cchr ). note 2: all timings are specified taking the levels of 20% and 80% of v dd as the reference. note 3: the values of t cclw and t cclr are specified during the overlapping period of cs1 at ?l? (cs2 = ?h?) and the ?l? levels of wr and rd , respectively. fedl9059e-01 lapis semiconductor ML9059E 10/72 ? s ystem bus write characteristics 2 (68-series mpu) ? system bus read characteristics 2 (68-series mpu) a0 c s 1 (cs2 = ?h?) e r/ w db0 to db7 (write) t aw6 t ds6 t dh6 t ewhw t ewlw t ah6 t cyc6 v ih v il v il v il v ih v il v il v il v ih v ih v il v ih v il v ih v il a0 c s 1 (cs2 = ?h?) e db0 to db7 (read) t aw6 t acc6 t ewhr t ewlr t ah6 t oh6 t cyc6 r/ w v il v il v ih v ih v il v ih v il v ih v il v ih v ih v oh v ol v oh v ol fedl9059e-01 lapis semiconductor ML9059E 11/72 [v dd = 4.5 to 5.5 v, tj = ?40 to +85c] rated value parameter symbol condition min max unit address hold time t ah6 5 ? address setup time t aw6 5 ? system cycle time t cyc6 166 ? data setup time t ds6 30 ? data hold time t dh6 10 ? access time t acc6 cl = 100 pf ? 70 output disable time t oh6 10 50 read t ewhr 70 ? enable h pulse width write t ewhw 30 ? read t ewlr 60 ? enable l pulse width write t ewlw 60 ? ns [v dd = 3.7 to 4.5 v, tj = ?40 to +85c] rated value parameter symbol condition min max unit address hold time t ah6 5 ? address setup time t aw6 5 ? system cycle time t cyc6 300 ? data setup time t ds6 40 ? data hold time t dh6 15 ? access time t acc6 ? 140 output disable time t oh6 cl = 100 pf 10 100 read t ewhr 120 ? enable h pulse width write t ewhw 60 ? read t ewlr 60 ? enable l pulse width write t ewlw 60 ? ns note 1: the input signal rise and fall times are specified as 15ns or less. when using the system cycle time for fast speed, the specified values are (tr + tf) ? (t cyc6 ? t ewlw ? t ewhw ) or (tr + tf) ? (t cyc6 ? t ewlr ? t ewhr ). note 2: all timings are specified taking the levels of 20% and 80% of v dd as the reference. note 3: the values of t ewlw and t ewlr are specified during the overlapping period of cs1 at ?l? (cs2 = ?h?) and the ?h? level of e. fedl9059e-01 lapis semiconductor ML9059E 12/72 serial interface timing characteristics ? serial in terface [v dd = 4.5 to 5.5 v, tj = ?40 to +85c] rated value parameter symbol condition min max unit serial clock period t scyc 200 ? scl ?h? pulse width t shw 75 ? scl ?l? pulse width t slw 75 ? address setup time t sas 50 ? address hold time t sah 100 ? data setup time t sds 50 ? data hold time t sdh 50 ? cs setup time t css 100 ? cs hold time t csh 100 ? ns note 1: the input signal rise and fall times are specified as 15ns or less. note 2: all timings are specified taking the levels of 20% and 80% of v dd as the reference. c s 1 (cs2 = ?1?) scl si a0 t css t slw t sds t shw t csh t sas t scyc t sah t sdh t f t r v il v ih v il v il v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih fedl9059e-01 lapis semiconductor ML9059E 13/72 [v dd = 3.7 to 4.5 v, tj = ?40 to +85c] rated value parameter symbol condition min max unit serial clock period t scyc 250 ? scl ?h? pulse width t shw 100 ? scl ?l? pulse width t slw 100 ? address setup time t sas 150 ? address hold time t sah 150 ? data setup time t sds 100 ? data hold time t sdh 100 ? cs setup time t css 150 ? cs hold time t csh 150 ? ns note 1: the input signal rise and fall times are specified as 15ns or less. note 2: all timings are specified taking the levels of 20% and 80% of v dd as the reference. ? display control output timing cl(out) fr t dfr v oh v ih v il [v dd = 4.5 to 5.5 v, tj = ?40 to +85c] rated value parameter symbol condition min typ max unit fr delay time t dfr cl = 50 pf ? 10 40 ns [v dd = 3.7 to 4.5 v, tj = ?40 to +85c] rated value parameter symbol condition min typ max unit fr delay time t dfr cl = 50 pf ? 20 80 ns note 1: all timings are specified taking the levels of 20% and 80% of v dd as the reference. note 2: valid only when the device operates in master mode. fedl9059e-01 lapis semiconductor ML9059E 14/72 ? r eset input timing [v dd = 4.5 to 5.5 v, tj = ?40 to +85c] rated value parameter symbol condition min typ max unit reset time t r ? ? 0.5 reset ?l? pulse width t rw 0.5 ? ? s [v dd = 3.7 to 4.5 v, tj = ?40 to +85c] rated value parameter symbol condition min typ max unit reset time t r ? ? 1 reset ?l? pulse width t rw 1 ? ? s note 1: the input signal rise and fall times (t r , t f ) are specified as 15 ns or less. note 2: all timings are specified taking the levels of 20% and 80% of v dd as the reference. r es internal state being reset reset complete t rw t r t f t r v ih v il v il v ih fedl9059e-01 lapis semiconductor ML9059E 15/72 pin description function pin name number of pins i/o description db0 to db7 8 i/o these are 8-bit bi-directional data bus pins that can be connected to 8-bit standard mpu data bus pins. when a serial interface is selected (p/ s = ?l?): db7: serial data input pin (si) db6: serial clock input pin (scl) in this case, db0 to db5 will be in the high impedance state. db0 to db7 will all be in the high impedance state when the chip select is in the inactive state. fix the db0 to db5 pins at ?h? or ?l? level. a0 1 i normally, the lowest bit of the mpu address bus is connected and used for distinguishing between data and commands. a0 = ?h?: indicates that db0 to db7 is display data. a1 = ?l?: indicates that db0 to db7 is control data. res 1 i initial setting is made by making res = ?l?. the reset operation is made during the active level of the res signal. cs1 cs2 2 i these are the chip select signals. the chip select of the lsi becomes active when cs1 is ?l? and also cs2 is ?h? and allows the input/output of data or commands. rd (e) 1 i the active level of this signal is ?l? when connected to an 80-series mpu. this pin is connected to the rd signal of the 80-series mpu, and the data bus of the ML9059E goes into the output state when this signal is ?l?. the active level of this signal is ?h? when connected to a 68-series mpu. this pin will be the enable and clock input pin when connected to a 68-series mpu. when a serial interface is selected (p/ s = ?l?), fix this pin at ?h? or ?l? level. wr (r/ w ) 1 i the active level of this signal is ?l? when connected to an 80-series mpu. this pin is connected to the wr signal of the 80-series mpu. the data on the data bus is latched into the ML9059E at the rising edge of the wr signal. when connected to a 68-series mpu, this pin becomes the input pin for the read/write control signal. r/ w = ?h?: read, r/ w = ?l?: write when a serial interface is selected (p/ s = ?l?), fix this pin at ?h? or ?l? level. mpu interface c86 1 i this is the pin for selecting the mpu interface type. c86 = ?h?: 68-series mpu interface. c86 = ?l?: 80-series mpu interface. fedl9059e-01 lapis semiconductor ML9059E 16/72 function pin name number of pins i/o description this is the pin for selecting parallel data input or serial data input. p/ s = ?h?: parallel data input. p/ s = ?l?: serial data input. the pins of the lsi have the following functions depending on the state of p/ s input. p/ s data/command data read/write serial clock ?h? a0 db0 to db7 rd , wr ? ?l? a0 si (d7) ? scl(db6) mpu interface p/ s 1 i during serial data input, it is not possible to read the display data in the ram oscillator circuit cls 1 i this is the pin for selecting whether to enable or disable the internal oscillator circuit for the display clock. cls = ?h?: the internal oscillator circuit is enabled. cls = ?l?: the internal oscillator circuit is disabled (external input). when cls = ?l?, the display clock is input at the pin cl. this is the pin for selecting whether master operation or slave operation is made towards the ML9059E. during slave operation, the synchronization with the lcd display system is achieved by inputting the timing signals necessary for lcd display. m/ s = ?h?: master operation m/ s = ?l?: slave operation the functions of the different circuits and pins will be as follows depending on the states of m/ s and cls signals. m/ s cls oscillator circuit power supply circuit cl fr frs dof ?h? enabled enabled output output output output ?h? ?l? disabled enabled input output output output ?h? disabled disabled input input output input ?l? ?l? disabled disabled input input output input display timing generator circuit m/ s 1 i fedl9059e-01 lapis semiconductor ML9059E 17/72 function pin name number of pins i/o description this is the clock input/output pin. the function of this pin will be as follows depending on the states of m/ s and cls signals. m/ s cls cl ?h? output ?h? ?l? input ?h? input ?l? ?l? input cl 1 i/o when the ML9059E is used in the master/slave mode, the corresponding cl pin has to be connected. fr 1 i/o this is the input/output pin for lcd display frame reversal signal. m/ s = ?h?: output m/ s = ?l?: input when the m l9059e is used in the master/slave mode, the corresponding fr pin has to be connected. dof 1 i/o this is the blanking control pin for the lcd display. m/ s = ?h?: output m/ s = ?l?: input when the m l9059e is used in the master/slave mode, the corresponding dof pin has to be connected. display timing generator circuit frs 1 o this is the output pin for static drive. this pin is used in combination with the fr pin. irs 1 i this is the pin for selecting the resistor for adjusting the voltage v1. irs = ?h?: the internal resistor is used. irs = ?l?: the internal resistor is not used. the voltage v1 is adjusted using the external potential divider resistors connected to the pins vr. this pin is effective only in the master operation. this pin is tied to the ?h? or the ?l? level during slave operation. v dd 12 ? these pins are tied to the mpu power supply pin v cc . v ss 12 ? these are the 0 v pins connected to the system ground (gnd). power supply circuit v in 5 ? these are the reference power supply pins of the voltage multiplier circuit for driving the lcd. fedl9059e-01 lapis semiconductor ML9059E 18/72 function pin name number of pins i/o description v rs 2 ? these are the test pins for the lcd power supply voltage adjustment circuit. leave these pins open. v out 2 i/o these are the output pins during voltage multiplication. connect a capacitor between these pins and v ss . these are the multiple level power supply pins for the lcd power supply. the voltages specified for the lcd cells are applied to these pins after resistor network voltage division or after impedance transformation using operational amplifiers. the voltages are specified taking v ss as the reference, and the following relationship should be maintained among them. v1 ? v2 ? v3 ? v4 ? v5 ? v ss master operation: when the power supply is on, the following voltages are applied to v2 to v5 from the built-in power supply circuit. the selection of voltages is determined by the lcd bias set command. ML9059E v2 7/8 ? v1 5/6 ? v1 v3 6/8 ? v1 4/6 ? v1 v4 2/8 ? v1 2/6 ? v1 v5 1/8 ? v1 1/6 ? v1 v1 v2 v3 v4 v5 10 i/o vr 2 i voltage adjustment pins. voltages between v1 and v ss are applied using a resistance voltage divider. these pins are effective only when the internal resistors for voltage v1 adjustment are not used (irs = ?l?). do not use these pins when the internal resistors for voltage v1 adjustment are used (irs = ?h?). vs1? 3 o these are the pins for connecting the negative side of the capacitors for voltage multiplication. connect capacitors between these pins and vc3+, vc5+. vs2? 3 o these are the pins for connecting the negative side of the capacitors for voltage multiplication. connect capacitors between these pins and vc4+, vc6+. vc3+ 3 o these are the input pins for voltage multiplication. apply the voltage equal to v in to the pins or leave them open, depending on voltage multiplication values. power supply circuit vc4+ 3 o these are the pins for connecting the positive side of the capacitors for voltage multiplication. connect capacitors between vs2? and these pins. for 3-time voltage multiplication, the pins are configured as inputs for voltage multiplication. fedl9059e-01 lapis semiconductor ML9059E 19/72 function pin name number of pins i/o description vc5+ 3 o these are the pins for connecting the positive side of the capacitors for voltage multiplication. connect capacitors between vs1? and these pins. for 2-time voltage multiplication, the pins are configured as inputs for voltage multiplication. power supply circuit vc6+ 3 o these are the pins for connecting the positive side of the capacitors for voltage multiplication. connect capacitors between vs2? and these pins. these are the lcd segment drive outputs. one of the levels among v1, v3, v4, and v ss is selected depending on the combination of the display ram content and the fr signal output voltage ram data fr forward display reverse display h h v1 v3 h l v ss v4 l h v3 v1 l l v4 v ss power save ? v ss seg0 to seg131 132 o the output voltage is v ss when the display off command is executed. these are the lcd common drive outputs. one of the levels among v1, v2, v5, and v ss is selected depending on the combination of the scan data and the fr signal. scan data fr output voltage h h v ss h l v1 l h v2 l l v5 power save ? v ss lcd drive output com0 to com47 48 o the output voltage is v ss when the display off command is executed. coms0 coms1 2 o these are the common output pins only for indicators. both pins output the same signal. leave these pins open when they are not used. the same signal is output in both master and slave operation modes. test pin test1 1 o these are the pins for testing the ic chip. leave these pins open during normal use. dummy 67 ? dummy- b 11 ? leave this pin open. fedl9059e-01 lapis semiconductor ML9059E 20/72 functional description mpu interface mpu read mode write mode 80-series pin rd = ?l? pin wr = ?l? pin r/ w = ?h? pin r/ w = ?l? 68-series pin e = ?h? pin e = ?h? in the case of the 80-series mpu interface, a command is started by applying a low pulse to the rd pin or the wr pin. in the case of the 68-series mpu interface, a command is started by applying a high pulse to the e pin. ? selection of interface type the ML9059E carries out data transfer using either the 8-bit bi-directional data bus (db0 to db7) or the serial data input line (si). either the 8-bit parallel data input or serial data input can be selected as shown in table 2 by setting the p/ s pin to the ?h? or the ?l? level. table 2 selection of interface type (parallel/serial) p/ s cs1 cs2 a0 rd wr c86 d7 d6 db0 to db5 h: parallel input l: serial input cs1 cs1 cs2 cs2 a0 a0 rd ? wr ? c86 ? d7 si d6 scl db0 to db5 ? a hyphen (?) indicates that the pin can be tied to the ?h? or the ?l? level. ? p arallel interface when the parallel interface is selected, (p/ s = ?h?), it is possible to connect this lsi directly to the mpu bus of either an 80-series mpu or a 68-series mpu as shown in table 3. depending on whether the pin c86 is set to ?h? or ?l?. table 3 selection of mpu during parallel interface (80?/68?series) c86 cs1 cs2 a0 rd wr db0 to db7 h: 68-series mpu bus l: 80-series mpu bus cs1 cs1 cs2 cs2 a0 a0 e rd r/ w wr db0 to db7 db0 to db7 the data bus signals are identified as shown in table 4 below depending on the combination of the signals a0, rd (e), and wr (r/ w ) of table 3. table 4 identification of data bus signals during parallel interface common 68-series 80-series a0 r/ w rd wr display data read display data write status read control data write (command) 1 1 0 0 1 0 1 0 0 1 0 1 1 0 1 0 fedl9059e-01 lapis semiconductor ML9059E 21/72 serial interface when the serial interface is selected (p/ s = ?l?), the serial data input (si) an d the serial clock input (scl) can be accepted if the chip is in the active state ( cs1 = ?l? and cs2 = ?h?). the serial interface consists of an 8-bit shift register and a 3-bit counter. the serial data is read in from the serial data input pin in the sequence db7, db6, ... , db0 at the rising edge of the serial clock input, and is convert ed into parallel data at the rising edge of the 8th serial clock pulse and processed further. the identification of whether the serial data is display data or command is judged based on the a0 input, and the data is treated as display data when a0 is ?h? and as command when a0 is ?l?. the a0 input is read in and identified at the rising edge of the (8 ? n) th serial clock pulse after the chip has become active. fig. 1 shows the signal chart of the serial interface. (when the chip is not active, the shift register and the counter are reset to their initial states. no data read out is possible in the case of the serial interface. it is necessary to take sufficient care about wiring termination reflection and external noise in the case of the scl signal. we recommend verification of operation in an actual unit.) fig. 1 signal chart during serial interface ? ch ip select the ML9059E has the two chip select pins cs1 and cs2, and the mpu interface or the serial interface is enabled only when cs1 = ?l? and cs2 = ?h?. when the chip select signals are in the inactive state, the db0 to db7 lines will be in the high impedance state and the inputs a0, rd , and wr will not be effective. when the serial interface has been selected, the shift register and the counter are rese t when the chip select signals are in the inactive state. ? a ccessing the display data ram and the internal registers accessing the ML9059E from the mpu side requires merely that the cycle time (t cyc ) be satisfied, and high speed data transfer without requiring any wait time is possible. also, during the data transfer with the mpu, the ML9059E carries out a type of pipeline processing between lsis via a bus holder associated with the internal data bus. for example, when the mpu writes data in the display data ram, the data is temporarily stored in the bus holder, and is then written into the display data ram before the next data read cycle. further, when the mpu reads out data in the display data ram, first a dummy data read cycle is carried out to temporarily store the data in the bus holder which is then placed on the system bus an d is read out during the next read cycle. there is a restriction on the read sequence of the display data ram, which is that the read instruction immediately after setting the address does not read out the data of that address, but that data is output as the data of the address specified during the second data read sequence, and hence care should be taken about this during reading. therefore, always one dummy read is necessary immediately after setting the address or after a write cycle: (the status read cannot use dummy read cycles.) this relationship is shown in figs 2(a) and 2(b). db7 si scl a0 cs2 c s1 1 db6 2 db5 3 db4 4 db3 5 db2 6 db1 7 db0 8 db7 9 db6 10 db5 11 db4 12 db3 13 db2 14 fedl9059e-01 lapis semiconductor ML9059E 22/72 ? data write fig. 2(a) write sequence of display data ram ? data read fig. 2(b) read sequence of display data ram dn = data n = address data ? busy flag the busy flag being ?1? indicates that the ML9059E is carrying out reset operations, and hence no instruction other than a status read instruction is accepted during this period. the busy flag is output at pin db7 when a status read instruction is executed. data bus holder dn latch dn + 1 w r mpu write signal internal timing dn + 2 dn + 3 dn dn + 1 dn + 2 dn + 3 data column address read signal address preset n unknown dn dn + 1 preset n unknown dn dn + 1 dn + 2 increment n + 1 n + 2 r d mpu w r bus holder internal timing address set n data read (dummy) data read dn data read dn + 1 fedl9059e-01 lapis semiconductor ML9059E 23/72 display data ram ? display data ram this is the ram storing the dot data for display and has an organization of 65 (8 pages ? 8 bits +1) ? 132 bits. it is possible to access any required bit by specifying the page address and the column address. since the display data db7 to db0 from the mpu corresponds to the lcd display in the direction of the common lines as shown in fig. 3, there are fewer restrictions during display data transfer when the ML9059E is used in a multiple chip configuration, thereby making it easily possible to realize a display with a high degree of freedom. also, since the display data ram read/write from the mpu side is carried out via an i/o buffer, it is done independent of the signal read operation for the lcd drive. consequently, the display is not affected by flickering, etc., even when the display data ram is accessed asynchronously during the lcd display operation. db0 0 1 1 1 ?? 0 com0 ? db1 1 0 0 0 ? 0 com1 ? db2 0 0 0 0 ? 0 com2 ? db3 0 1 1 1 ? 0 com3 ? db4 1 0 0 0 ? 0 com4 ? display data ram lcd display fig. 3 relationship between display data ram and lcd display ? page address circuit the page address of the display data ram is specified using the page address set command as shown in fig. 4. specify the page address again when accessing after changing the page. the page address 8 (db3, db2, db1, db0 ? 1, 0, 0, 0) is the ram area dedicated to the indicator, and only the display data db0 is valid in this page. ? co lumn address circuit the column address of the display data ram is specified using the column address set command as shown in fig. 4. since the specified column address is incremented (b y +1) every time a display data read/write command is issued, the mpu can access the display data continuously. further, the incrementing of the column address is stopped at the column address of 83(h). since the column address and the page address are independent of each other, it is necessary, for example, to specify separately the new page address and the new column address when changing from column 83(h) of page 0 to column 00(h) of page 1. also, as is shown in table 5, it is possible to reverse the correspondence relationship between the display data ram column address and the segment output using the adc command (the segment driver direction select command). this reduces the ic placement restrictions at the time of assembling lcd modules. table 5 correspondence relationship between the display data ram column address and the segment output segment output adc seg0 seg131 db0 = ?0? 0(h) ? ? column address ? 83(h) db0 = ?1? 83(h) ? ? column address ? 0(h) fedl9059e-01 lapis semiconductor ML9059E 24/72 ? l ine address circuit the line address circuit is used for specifying the lin e address corresponding to the common output when displaying the contents of the display data ram as is shown in fig. 4. normally, the topmost line in the display is specified using the display start line address set command (com0 output in the forward display state of the common output, and com47 output in the reverse display state). the display area is 48 lines in the direction of increasing line address from the specified display start li ne address. when the indi cator?dedicated common output pin (coms) is selected, data in line address 40 h = page 8 and bit 0 is displayed irrespective of the display start line address. coms selection is 49th in order. it is possible to carry out screen scrolling by dynamically changing the line address using the display start line address set command. ? disp lay data latch circuit the display data latch circuit is a latch for temporarily storing the data from the display data ram before being output to the lcd drive circuits. since the commands for selecting forward/reverse display and turning the display on/off control the data in this latch, the data in the display data ram will not be changed. oscillator circuit t his is an rc oscillator that generates the display clock. the oscillator circuit is effective only when m/ s = ?h? and also cls = ?h?. the oscillations will be stopped when cls = ?l?, and the display clock has to be input to the cl pin. fedl9059e-01 lapis semiconductor ML9059E 25/72 fig. 4 display data ram address map db0 page address data line a ddress com output when the common output state is normal display db1 db2 db3 db4 db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 db0 00h com0 com1 com2 48 lines (start) com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 coms the 40(h) is displayed irrespective of the display start line address. 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh 40h seg131 page0 page1 page2 page3 page4 page5 page6 page7 page8 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 seg130 seg0 seg129 seg1 seg128 seg2 seg127 seg3 seg7 seg4 seg6 seg5 lcd output 1 0 db0 db0 adc column address 00(h) 01(h) 02(h) 03(h) 04(h) 05(h) 06(h) 07(h) 7f(h) 80(h) 81(h) 82(h) 83(h) 83(h) 82(h) 81(h) 80(h) 7f(h) 7e(h) 7d(h) 7c(h) 04(h) 03(h) 02(h) 01(h) 00(h) fedl9059e-01 lapis semiconductor ML9059E 26/72 display timing generator circuit this circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. the display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. this circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. the display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. the read out of the display data to the lcd drive circuits is completely independent of the display data ram access from the mpu. as a result, there is no bad influence such as flickering on the display even when the display data ram is accessed asynchronously during the lcd display. also, the internal common timing and lcd frame reversal (fr) signals are generated by this circuit from the display clock. the drive waveforms of the frame reversal drive method shown in fig. 5(a) for the lcd drive circuits are generated by this circuit. the drive waveforms of the line reversal drive method shown in fig. 5(b) are also generated by the command. ram data v ss v5 com1 48 49 1 2 3 4 5 6 v2 v1 v ss v4 segn v3 v1 44 45 46 47 48 49 1 23 4 5 6 v ss v5 com0 v2 v1 f r lcdc k (display clock) fig. 5(a) waveforms in the frame reversal drive method fedl9059e-01 lapis semiconductor ML9059E 27/72 ram data v ss v5 com1 v2 v1 v ss v4 segn v3 v1 v ss v5 com0 v2 v1 48 1 2 3 4 5 6 44 45 46 47 48 49 1 2 3 4 5 6 lcdc k (display clock) fr 49 fig. 5(b) waveforms in the line reversal drive method when the ML9059E is used in a multiple chip configuration, it is necessary to supply the slave side display timing signals (fr, cl, and dof ) from the master side. however, when the line reversal drive is set, the ML9059E is not used in a multiple chip configuration. the statuses of the signals fr, cl, and dof are shown in table 6. table 6 display timing signals in master mode and slave mode operating mode fr cl dof internal oscillator circuit enabled (cls = h) output output output master mode (m/ s = ?h?) internal oscillator circuit disabled (cls = l) output input output internal oscillator circuit disabled (cls = h) input input input slave mode (m/ s = ?l?) internal oscillator circuit disabled (cls = l) input input input note: during master mode, the oscillator circuit operates from the time the power is applied. the oscillator circuit can be stopped only in the sleep state. fedl9059e-01 lapis semiconductor ML9059E 28/72 common output state selection circuit (see table 7) si nce the common output scanning directions can be set using the common output state selection command in the ML9059E, it is possible to reduce the ic placement restrictions at the time of assembling lcd modules. table 7 common output state settings state common scanning direction forward display com0 ? com47 reverse display com47 ? com0 lcd drive circuit t his lsi incorporates 181 sets of multiplexers for the ML9059E, that generate 4-level outputs for driving the lcd. these output the lcd drive voltage in accordance with the combination of the display data, common scanning signals, and the fr signal. fig. 6 shows examples of the segment and common output waveforms in the frame reversal drive method. static indicator circuit t he fr pin is connected to one side of the lcd drive electrode of the static indicator and the frs pin is connected to the other side. the static indicator display is controlled by a command only independently of other display control commands. the electrode of the static indicator should has a wiring pattern that is distant from the dynamic drive electrode. if the wiring pattern is placed too near to the dynami c drive electrode, the lcd and electrode may be degraded. fedl9059e-01 lapis semiconductor ML9059E 29/72 fig. 6 output waveforms in the frame reversal drive method (fr waveform/common waveform/segment waveform/voltage difference between common and segment) com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 fr com0 com1 com2 seg0 seg1 seg2 com0-seg0 com0-seg1 v dd v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 0v -v5 -v4 -v3 -v2 -v1 v1 v2 v3 v4 v5 0v -v5 -v4 -v3 -v2 -v1 seg0 seg1 seg2 seg3 seg4 fedl9059e-01 lapis semiconductor ML9059E 30/72 power supply circuit t his is the low power consumption type power supply circuit for generating the voltages necessary for driving lcd devices, and consists of voltage multiplier circuits, vo ltage adjustment circuits, and voltage follower circuits. in the power supply circuit, it is possible to control the on/off of each of the circuits of the voltage multiplier, voltage adjustment circuits, and voltage follower circuits using the power control set command. as a result, it is also possible to use parts of the functions of both the external power supply and the internal power supply. table 8 shows the functions controlled by the 3-bit data of the power control set command and table 9 shows a sample combination. table 8 details of functions controlled by the bits of the power control set command control bit function controlled by the bit db2 voltage multiplier circuit control bit db1 voltage adjustment circuit (v1 voltage adjustment circuit) control bit db0 voltage follower circuit (v/f circuit) control bit table 9 sample combination for reference circuit state used db2 db1 db0 voltage multiplier v adjustment v/f external voltage input voltage multiplier pins *1 only the internal power supply is used 1 1 1 ? v in used only v adjustment and v/f circuits are used 0 1 1 ?? v out open only v/f circuits are used 0 0 1 ? ? v1 open only the external power supply is used 0 0 0 ? ? ? v1 to v5 open *1: the voltage multiplier pins are the pins vs1?, vs2?, vc3+, vc4+, vc5+, and vc6+. if combinations other than the above are used, normal operation is not guaranteed. fedl9059e-01 lapis semiconductor ML9059E 31/72 ? vo ltage multiplier circuits the connections for 2- to 4-time voltage multiplier circuits are shown below. v in v ss v out vc6+ vc4+ vs2? vc5+ vc3+ vs1? 2-time voltage multiplier circuit open v in v ss v out vc6+ vc4+ vs2? vc5+ vc3+ vs1? v in v ss v out vc6+ vc4+ vs2? vc5+ vc3+ vs1? 4-time voltage multiplier circuit open open 3-time voltage multiplier circuit + + ++ + + + + + fig. 7 connection examples for voltage multiplier circuits fedl9059e-01 lapis semiconductor ML9059E 32/72 the voltage relationships in voltage multiplication are shown in fig. 8. v out = 3 ? v in = 15.0 v *1 v in = 5.0 v v ss = 0 v v out = 4 ? v in = 18 v *1 v in = 4.5 v v ss = 0 v voltage relationship in 3-time multiplication voltage relationship in 4-time multiplication fig. 8 voltage relationship s in voltage multiplication *1: the voltage range of v in should be set from 6v to 18.33v so that the voltage at the pin v out does not exceed the voltage multiplier output voltage operating range. ? voltage adjustment circuit the voltage multiplier output v out produces the lcd drive voltage v1 via the voltage adjustment circuit. since the ML9059E incorporates a high accuracy constant voltage generator, a 64-level electronic potentiometer function, and also resistors for voltage v1 adjustment, it is possible to build a high accuracy voltage adjustment circuit with very few components. in addition, the ml 9059e is available with the temperature gradients of a vreg - about ?0.05%/c. (a) when the internal resistors for voltage v1 adjustment are used it is possible to control the lcd power supply voltage v1 and adjust the intensity of lcd display using commands and without needing any external resistors, if the internal voltage v1 adjustment resistors and the electronic potentiometer function are used. the voltage v1 can be obtained by the following equation a-1 in the range of v1 fedl9059e-01 lapis semiconductor ML9059E 34/72 (b) when external resistors are used (voltage v1 adjustment internal resistors are not used) it is also possible to set the lcd drive power supply voltage v1 without using the internal resistors for voltage v1 adjustment but connecting external resistors (ra' and rb') between v ss & vr and between vr & v1. even in this case, it is possible to control the lcd power supply voltage v1 and adjust the intensity of lcd display using commands if the electronic potentiometer function is used. the voltage v1 can be obtained by the following equation b-1 in the range of v1 fedl9059e-01 lapis semiconductor ML9059E 37/72 * when using the voltage v1 adjustment internal resistor s or the electronic potentiometer function, it is necessary to set at least the voltage adjustment circuit and the voltage follower circuits both in the operating state using the power control setting command. also, when the voltage multiplier circuit is off, it is necessary to supply a voltage externally to the v out pin. * the pin vr is effective only when the voltage v1 adjustment internal resistors are not used (pin irs = ?l?). leave this pin open when the voltage v1 adjustment internal resistors are being used (pin irs = ?h?). * since the input impedance of the pin vr is high, it is necessary to take noise countermeasures such as using short wiring length or a shielded wire . * the supply current increases in proportion to the pane l capacitance. when power consumption increases, the v out level may fall. the voltage (v out ? v1) should be more than 3 v. ? lcd drive voltage generator circuits the voltage v1 is divided using resistors inside the ic to generate the voltages v2, v3, v4, and v5 that are necessary for driving the lcd. in addition, these voltages v2, v3, v4, and v5 are impedance transformed using voltage follower circuits and fed to the lcd drive circuits. the bias ratio of 1/8 or 1/6 can be selected using the lcd bias setting command. ? a t built-in power-on, and transition from power save state to display mode after built-in power-on, at the command "2f(h)" input, or on transition from power save state to display mode, the display does not operate for a maximum period of 300 ms until the built-in power is stabilized. this period of no display is not influenced by display on/off command. despite input of display on command during this period, the display does not operate for this period. however, the command is valid. after the wait time is finished, the display operates. (during this period of no display, all commands are acceptable.) ? c ommand sequence for shutting off the internal power supply when shutting off the internal power supply, it is recomme nded to use the procedure given in fig. 12 of switching off the power after putting the lsi in the power save state using the following command sequence. procedure description commands (command, status) db7 db6 db5 db4 db3 db2 db1 db0 step1 display off 1 0 1 01110 power save commands ?? ?? (multiple commands) step2 display all on 1 0 1 00101 ?? ?? end internal power supply off fig. 12 command sequence for shutting off the internal power supply fedl9059e-01 lapis semiconductor ML9059E 38/72 ? a pplication circuits (two v1 pins are described in the following examples for explanation, but they are the same.) (2) when the voltage multiplier circuit, voltage adjustment circuit, and v/f circuits are all used when not using the internal voltage v1 adjustment resistors v in = v dd 3-time voltage multiplication (4) when only the voltage adjustment circuit and v/f circuits are used when using the internal voltage v1 adjustment resistors (1) when the voltage multiplier circuit, voltage adjustment circuit, and v/f circuits are all used when using the internal voltage v1 adjustment resistors v in = v dd 3-time voltage multiplication (3) when only the voltage adjustment circuit and v/f circuits are used when not using the internal voltage v1 adjustment resistors irs v in v c6+ v c4+ v s2 ? v c5+ v c3+ v s1 ? v 1 v r v ss v out v 1 v 2 v 3 v 4 v 5 m/ s v dd v ss c1: *1 c2: *2 c1 c1 c1 c1 c2 c2 c2 c2 open + + + + + + + + open irs v in v c6+ v c4+ v s2 ? v c5+ v c3+ v s1 ? v 1 v r v ss v out v 1 v 2 v 3 v 4 v 5 m/ s v dd v ss c1 c1 c2 c2 c2 c2 r 1 r 2 r 3 c1:*1 c1 c1 open rall=r1+r2+r3 rall: *3 + + + + + + + + c2: *2 irs v in v c6+ v c4+ v s2 ? v c5+ v c3+ v s1 ? v 1 v r v ss v out v 1 v 2 v 3 v 4 v 5 m/ s v dd v ss c1 c2 c2 c2 c2 r 1 r 2 r 3 external power supply c1: *1 c2: *2 + + + + + open open open open open open rall=r1+r2+r3 rall: *3 irs v in v c6+ v c4+ v s2 ? v c5+ v c3+ v s1 ? v 1 v r v ss v out v 1 v 2 v 3 v 4 v 5 m/ s v dd v ss c1 c2 c2 c2 c2 external power supply c1: *1 c2: *2 + + + + + open open open open open open open fedl9059e-01 lapis semiconductor ML9059E 39/72 note: when trace resistance external to cog-mounted chip does not exist, ? when c1 (*1) = 0.9 p f to 5.7 p f, c2 (*2) = 0.42 p f to 1.2 p f, use in the range rall (*3) = 1 m : to 5 m : . ? when c1 (*1) = 1.8 p f to 5.7 p f, c2 (*2) = 0.42 p f to 1.2 p f, use in the range rall (*3) = 500 k : to 1 m : . make sure that voltage multiplier output voltage, and v1 output voltage have enough margin before using this lsi. x in itial setting note: if electric charge remains in smoothing capacitor co nnected between the lcd driver voltage output pins (v1 to v5) and the v ss pin, a malfunction might occur: the display screen gets dark for an instant when powered on. to avoid a malfunction at power-on, it is recomme nded to follow the flowchart in the ?examples of settings for the instructions? section in page 54. (6) when not using the internal power supply (5) when only the v/f circuits are used v ss c2: *2 c2 c2 c2 c2 irs v in vc6+ vc4+ vs2? vc5+ vc3+ vs1? v1 vr v ss v out v1 v2 v3 v4 v5 m/ s v dd external power supply open open open open open open open open irs v in vc6+ vc4+ vs2? vc5+ vc3+ vs1? v1 vr v ss v out v1 v2 v3 v4 v5 m/ s v dd v ss external power supply open open open open open open open open + + + + fedl9059e-01 lapis semiconductor ML9059E 40/72 list of operation dbn no operation 7 6 5 4 3 2 1 0 a0 rd wr comment display off 1 0 1 0 1 1 1 0 0 1 0 1 display on 1 0 1 0 1 1 1 1 0 1 0 lcd display: off when db0 = 0 on when db0 = 1 2 display start line set 0 1 address 0 1 0 the display starting line address in the display ram is set. 3 page address set 1 0 1 1 address 0 1 0 the page address in the display ram is set. column address set (upper bits) 0 0 0 1 address (upper) 0 1 0 the upper 4 bits of the column address in the display ram is set. 4 column address set (lower bits) 0 0 0 0 address (lower) 0 1 0 the lower 4 bits of the column address in the display ram is set. 5 status read status * * * * 0 0 1 the status information is read out from the upper 4 bits. 6 display data write write data 1 1 0 writes data to the display data ram. 7 display data read read data 1 0 1 reads data from the display data ram. forward 1 0 1 0 0 0 0 0 0 1 0 8 adc select reverse 1 0 1 0 0 0 0 1 0 1 0 correspondence to the segment output for the display data ram address forward when db0 = 0 reverse when db0 = 1 forward 1 0 1 0 0 1 1 0 0 1 0 9 display reverse 1 0 1 0 0 1 1 1 0 1 0 forward or reverse lcd display mode forward when db0 = 0 reverse when db0 = 1 off (normal display) 1 0 1 0 0 1 0 0 0 1 0 10 lcd all-on display on 1 0 1 0 0 1 0 1 0 1 0 lcd normal display when db0 = 0 all-on display when db0 = 1 1 0 1 0 0 0 1 0 0 1 0 11 lcd bias set 1 0 1 0 0 0 1 1 0 1 0 sets the lcd drive voltage bias ratio. 1/8 when db0 = 0 and 1/6 when db0 = 1 12 read-modify-write 1 1 1 0 0 0 0 0 0 1 0 incrementing column address during a write: +1 during a read: 0 13 end 1 1 1 0 1 1 1 0 0 1 0 releases the read-modify-write state. 14 reset 1 1 1 0 0 0 1 0 0 1 0 internal reset 1 1 0 0 0 * * * 0 1 0 15 common output state select 1 1 0 0 1 * * * 0 1 0 selects the common output scanning direction. forward when db3 = 0 reverse when db3 = 1 16 power control set 0 0 1 0 1 operating state 0 1 0 selects the operating state of the internal power supply. set the lower 3 bits. 17 voltage v1 adjustment internal resistance ratio set 0 0 1 0 0 resistance ratio setting 0 1 0 selects the internal resistor ratio. set the lower 3 bits. fedl9059e-01 lapis semiconductor ML9059E 41/72 dbn no operation 7 6 5 4 3 2 1 0 a0 rd wr comment electronic potentiometer mode set 1 0 0 0 0 0 0 1 0 1 0 18 electronic potentiometer electronic potentiometer register set * * electronic potentiometer value 0 1 0 sets a 6-bit data in the electronic potentiometer register to adjust the v1 output voltage. (2-byte command) off 1 0 1 0 1 1 0 0 0 1 0 off when db0 = 0 static indicator on 1 0 1 0 1 1 0 1 0 1 0 19 static indicator register set * * * * * * state 0 1 0 on when db0 = 1 sets the blinking state. (2-byte command) 1 1 0 1 0 * * * 0 1 0 frame reversal when db3 = 0. lcd drive method set 1 1 0 1 1 * * * 0 1 0 20 1) line reversal number set * * * number of lines 0 1 0 line reversal when db3 = 1 sets the number (2-byte command) of line reversal. 21 power save compound command of display off and display all-on. 22 nop 1 1 1 0 0 0 1 1 0 1 0 the ?no operation? command. 23 test 1 1 1 1 * * * * 0 1 0 the command for factory testing of the ic chip. *: invalid data (input: don?t care, output: unknown) note 1: when the line reversal drive is set, the ML9059E is not used in a multiple chip configuration. fedl9059e-01 lapis semiconductor ML9059E 42/72 descriptions of operation display on/off (write) t his is the command for controlling the turning on or off the lcd panel. the lcd display is turned on when a ?1? is written in bit db0 and is turned off when a ?0? is written in this bit. a0 db7 db6 db5 db4 db3 db2 db1 db0 display on 0 1 0 1 0 1 1 1 1 display off 0 1 0 1 0 1 1 1 0 display start line set (write) t his command specifies the display starting line address in the display data ram. normally, the topmost line in the display is specified using the display start line set command. it is possible to scroll the display screen by dynamically changing the address using the display start line set command. line address a0 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 2 0 0 1 0 0 0 0 1 0 ? ? ? ? ? ? ? ? ? ? 62 0 0 1 1 1 1 1 1 0 63 0 0 1 1 1 1 1 1 1 fedl9059e-01 lapis semiconductor ML9059E 43/72 page address set (write) t his command specifies the page address which corresponds to the lower address when accessing the display data ram from the mpu side. it is possible to access any required bit in the display data ram by specifying the page address and the column address. page address a0 db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 0 0 0 0 1 0 1 0 1 1 0 0 0 1 2 0 1 0 1 1 0 0 1 0 ? ? ? ? ? ? ? ? ? ? 7 0 1 0 1 1 0 1 1 1 8 0 1 0 1 1 1 0 0 0 note: do not specify values that do not exist as an address. column address set (write) t his command specifies the column address of the display data ram. the column address is specified by successively writing the upper 4 bits and the lower 4 bits. since the column address is automatically incremented (by + 1) every time the display data ram is accessed, the mpu can read or write the display data continuously. the incrementing of the column address is stopped at the address 83(h). a0 db7 db6 db5 db4 db3 db2 db1 db0 upper bits 0 0 0 0 1 a7 a6 a5 a4 lower bits 0 0 0 0 0 a3 a2 a1 a0 column address a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 ? ? ? ? ? ? ? ? ? 130 1 0 0 0 0 0 1 0 131 1 0 0 0 0 0 1 1 note: do not specify values that do not exist as an address. fedl9059e-01 lapis semiconductor ML9059E 44/72 status read (read) a0 db7 db6 db5 db4 db3 db2 db1 db0 0 busy adc on/off reset * * * * *: invalid data busy when busy is '1', it indicates that the internal operations are being made or the lsi is being reset. although no command is accepted until busy becomes '0', there is no need to check this bit if the cycle time can be satisfied. adc this bit indicates the relationship between the column address and the segment driver. 0: reverse (seg131 ? seg0); column address 0(h) ? 83(h) 1: forward (seg0 ? seg131); column address 0(h) ? 83(h) (opposite to the polarity of the adc command.) on/off this bit indicates the on/off state of the display. (opposite to the polarity of the display on/off command.) 0: display on 1: display off reset this bit indicates that the lsi is being reset due to the res signal or the reset command. 0: operating state 1: being reset display data write (write) t his command writes an 8-bit data at the specified address of the display data ram. since the column address is automatically incremented (by +1) after writing the data, the mpu can write successive display data to the display data ram. a0 db7 db6 db5 db4 db3 db2 db1 db0 1 write data display data read (read) t his command read the 8-bit data from the specified addre ss of the display data ram. since the column address is automatically incremented (by +1) after reading the data, the mpu can read successive display data from the display data ram. further, one dummy read operation is necessary immediately after setting the column data. the display data cannot be read out when the serial interface is being used. a0 db7 db6 db5 db4 db3 db2 db1 db0 1 read data fedl9059e-01 lapis semiconductor ML9059E 45/72 adc select (segment driver direction select) (write) usin g this command it is possible to reverse the relationship of correspondence between the column address of the display data ram and the segment driver output. it is possible to reverse the sequence of the segment driver output pin by the command. a0 db7 db6 db5 db4 db3 db2 db1 db0 forward 0 1 0 1 0 0 0 0 0 reverse 0 1 0 1 0 0 0 0 1 forward/reverse display mode (write) it is p ossible to toggle the display on and off condition without changing the contents of the display data ram. in this case, the contents of the display data ram will be retained. a0 db7 db6 db5 db4 db3 db2 db1 db0 ram data forward 0 1 0 1 0 0 1 1 0 display on when ?h? reverse 0 1 0 1 0 0 1 1 1 display on when ?l? lcd display all-on on/off (write) usin g this command, it is possible to forcibly turn on all the dots in the display irrespective of the contents of the display data ram. in this case, the contents of the display data ram will be retained. this command is given priority over the forward/reverse display mode command. a0 db7 db6 db5 db4 db3 db2 db1 db0 all-on display off (normal display) 0 1 0 1 0 0 1 0 0 all-on display on 0 1 0 1 0 0 1 0 1 the power save mode will be entered into when the display all-on on command is executed in the display off condition. lcd bias set (write) t his command is used for selecting the bias ratio of the voltage necessary for driving the lcd device or panel. lcd bias a0 db7 db6 db5 db4 db3 db2 db1 db0 1/8 bias 0 1 0 1 0 0 0 1 0 1/6 bias 0 1 0 1 0 0 0 1 1 fedl9059e-01 lapis semiconductor ML9059E 46/72 read modify write (write) t his command is used in combination with the end comm and. when this command is issued once, the column address is not changed when the display data read command is issued, but is incremented (by +1) only when the display data write command is issued. this condition is maintained until the end command is issued. when the end command is issued, the column address is restored to the address that was effective at the time the read-modify-write command was issued last. using this function, it is possible to reduce the overhead on the mpu when repeatedly changing the data in special display area such as a blinking cursor. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 1 1 0 0 0 0 0 end (write) t his command releases the read-modify-write mode and rest ores the column address to the value at the beginning of the mode. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 1 1 0 1 1 1 0 read-modify-write mode set n n+1 n+2 n + 3 .... n+m n column address end restored reset (write) t his command initializes the display start line number, column address, page address, common output state, voltage v1 adjustment internal resistor ratio, electronic potentiometer function, and the static indicator function, and also releases the read-modify-write mode or the test mode. this command does not affect the contents of the display data ram. the reset operation is made after issuing the reset command. the initialization after switching on the power is carried out by the reset signal input to the res pin. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 1 1 0 0 0 1 0 common output state select (write) t his command is used for selecting the scanning direction of the common output pins. scanning direction a0 db7 db6 db5 db4 db3 db2 db1 db0 forward com0 ? com47 0 1 1 0 0 0 * * * reverse com47 ? com0 0 1 1 0 0 1 * * * *: invalid data fedl9059e-01 lapis semiconductor ML9059E 47/72 power control set (write) t his command set the functions of the power supply circuits. a0 db7 db6 db5 db4 db3 db2 db1 db0 voltage multiplier circuit: off voltage multiplier circuit: on 0 0 0 0 0 0 1 1 0 0 1 1 0 1 voltage adjustment circuit: off voltage adjustment circuit: on 0 0 0 0 0 0 1 1 0 0 1 1 0 1 voltage follower circuits: off voltage follower circuits: on 0 0 0 0 0 0 1 1 0 0 1 1 0 1 voltage v1 adjustment internal resistor ratio set t his command sets the ratios of the internal resistors for adjusting the voltage v1. resistor ratio a0 db7 db6 db5 db4 db3 db2 db1 db0 3.0 0 0 0 1 0 0 0 0 0 3.5 0 0 0 1 0 0 0 0 1 4.0 0 0 0 1 0 0 0 1 0 4.5 0 0 0 1 0 0 0 1 1 5.0 0 0 0 1 0 0 1 0 0 5.5 0 0 0 1 0 0 1 0 1 6.0 0 0 0 1 0 0 1 1 0 input inhibiting code 0 0 0 1 0 0 1 1 1 note: because this lsi has temperature gradient, v1 rises at lower temperatures. when using v1 gain of 6 times, adjust the built-in electronic potentiometer so that v1 does not exceed 18 v. electronic potentiome ter (2-byte co mmand) this command is used for controlling the lcd drive voltage v1 output by the voltage adjustment circuit of the internal lcd power supply and for adjusting the intensity of the lcd display. this is a two-byte command consisting of the electronic potentiometer mode set command and the electronic potentiometer register set command, both of which should always be issued successively as a pair. ? electro nic potentiometer mode set (write) when this command is issued, the electronic potentiometer register set command becomes effective. once the electronic potentiometer mode is set, it is not possible to issue any command other than the electronic potentiometer register set command. this condition is released after data has been set in the register using the electronic potentiometer register set command. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 0 0 0 0 1 fedl9059e-01 lapis semiconductor ML9059E 48/72 ? electron ic potentiometer register set (write) by setting a 6-bit data in the electronic potentiometer register using this command, it is possible to set the lcd drive voltage v1 to one of the 64 voltage levels. the electronic potentiometer mode is released after some data has been set in the electronic potentiometer register using this command. ?? a0 db7 db6 db5 db4 db3 db2 db1 db0 63 0 * * 0 0 0 0 0 1 62 0 * * 0 0 0 0 0 1 61 0 * * 0 0 0 0 1 0 60 0 * * 0 0 0 0 1 1 ? ? ? ? ? ? ? ? ? ? 1 ? ? ? 1 1 1 1 1 0 0 0 * * 1 1 1 1 1 1 *: invalid data set the data (*, *, 1, 0, 0, 0, 0, 0) when not using the electronic potentiometer function. sequence of setting the electronic potentiometer register: static indicator (2-byte command) t his command is used for controlling the static drive type indicator display. static indicator display is controlled only by this command and is independent of all other display control commands. since the static indicator on command is a two-byte command used in combination with the static indictor register set command, these two commands should always be used together. (the static indicator off command is a single byte command.) electronic potentiometer mode set electronic potentiometer register set the electronic potentiometer mode is released fedl9059e-01 lapis semiconductor ML9059E 49/72 ? static i ndicator on/off (write) when the static indicator on command is issued, the stat ic indicator register set command becomes effective. once the static indicator on command is issued, it is no t possible to issue any command other than the static indicator register set command. this condition is released only after some data is written into the register using the static indicator register set command. static indicator a0 db7 db6 db5 db4 db3 db2 db1 db0 off 0 1 0 1 0 1 1 0 0 on 0 1 0 1 0 1 1 0 1 ? static i ndicator register set (write) this command is used to set data in the 2-bit static indicator register thereby setting the blinking state of the static indicator. indicator a0 db7 db6 db5 db4 db3 db2 db1 db0 off 0 * * * * * * 0 0 on(blinking at about 1sec intervals) 0 * * * * * * 0 1 on(blinking at about 0.5sec intervals) 0 * * * * * * 1 0 on(continuously on) 0 * * * * * * 1 1 *: invalid data sequence of setting the static indicator register: static indicator on static indicator register set the static indicator mode is released fedl9059e-01 lapis semiconductor ML9059E 50/72 lcd drive method set (write) t his command sets the lcd drive method. ? l ine reversal drive (2-byte command)/frame reversal drive select line or frame reversal drive can be selected as the lcd drive method. when selecting line reversal drive, which is 2-byte command used with line reversal number set command, be sure to use both commands successively. once line reversal drive is set, commands other than line reversal number set command cannot be used. this state is released after data is set to the register by line reversal number set command. the frame reversal set command is a single byte command. lcd drive method a0 db7 db6 db5 db4 db3 db2 db1 db0 frame reversal 0 1 1 0 1 0 * * * line reversal 0 1 1 0 1 1 * * * *: invalid data ? l ine reversal number set (write) the number of lines is set when the line reversal is set using the lcd drive method set command. number of line reversal a0 db7 db6 db5 db4 db3 db2 db1 db0 1 0 * * * 0 0 0 0 0 2 0 * * * 0 0 0 0 1 3 0 * * * 0 0 0 1 0 4 0 * * * 0 0 0 1 1 ? ? ? ? ? ? ? ? ? ? 31 ? ? ? ? 1 1 1 1 0 32 0 * * * 1 1 1 1 1 *: invalid data note 1: because the number of line reversal depends on panel size and panel load capacitance, set the optimum number of lines at the time of es evaluation. note 2: when line reversal drive is used, a multiple chip configuration cannot be achieved. lcd drive method set number of line is set in case of line reversal fedl9059e-01 lapis semiconductor ML9059E 51/72 power save (compound command) t he lsi goes into the power save state when the display all-on on command is issued when the lsi is in the display off state, and it is possible to greatly reduce the current consumption in this state. the power save state is of two types, namely, the sleep state and the standby state, and the lsi goes into the standby state when the static indicator has been made on. the display data and the operating mode just before entering the power save mode are retained in both the sleep state and the standby state, and also the mpu can access the display data ram and other registers in these states. the power save mode is released by issuing the display all-on off command. (see the following figure.) static indicator off power save command issue (compound command) sleep state power save off command (display all-on off command) sleep state released static indicator on standby state power save off command (display all-on off command) standby state released fedl9059e-01 lapis semiconductor ML9059E 52/72 ? sleep s tate in this state, all the operations of the lcd display system are stopped and it is possible to reduce the current consumption to a level near the idle state current c onsumption unless there are accesses from the mpu. the internal conditions in the sleep state are as follows: (1) the oscillator circuit and the lcd power supply are stopped. (2) all the lcd drive circuits are stopped and the segment and common driver outputs will be at the v ss level. ? stan dby state all operations of the dynamic lcd display section are stopped, only the static display circuits for the indicators operate and hence the current consumption will be the minimum necessary for static drive. the internal conditions in the standby state are as follows: (1) the power supply circuit for lcd drive is stopped. the oscillator circuit will be operating. (2) the lcd drive circuits for dynamic display are stopped and the segment and common driver outputs will be at the v ss level. the static display section will be operating. note: when using an external power supply, stop external power supply at power save start-up. for example, when providing each level of lcd drive voltage with external voltage divider, add a circuit for cutting off current flowing through the resistors of the voltage divider when initiating power save. the ML9059E has lcd display blanking control pin, dof , which goes "l" at power save start-up. the external power supply can be stopped using dof output. nop (write) t his is a no operation command. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 1 1 0 0 0 1 1 test (write) t his is a command for testing the ic chip. do not use this command. when the test command is issued by mistake, this state can be released by issuing a nop command. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 1 1 1 * * * * *: invalid data fedl9059e-01 lapis semiconductor ML9059E 53/72 initialized condition using the res pin this lsi goes into the initialized condition when the res input goes to the ?l? level. the initialized condition consists of the following conditions. (1) display off (2) forward display mode (3) adc select: incremented (adc command db0 = ?l?) (4) power control register: (db2, db1, db0) = (0, 0, 0) (5) the registers and data in the serial interface are cleared. (6) lcd power supply bias ratio: 1/8 bias (7) all display dots off (8) read-modify-write: off (9) static indicator: off static indicator register: (db1, db0) = (0, 0) (10) line 1 is set as the display start line. (11) the column address is set to address 0. (12) the page address is set to 0. (13) common output state: forward (14) voltage v1 adjustment internal resistor ratio register: (db2, db1, db0) = (1, 0, 0) (15) the electronic potentiometer register set mode is released. electronic potentiometer register: (db5, db4, db3, db2, db1, db0) = (1, 0, 0 ,0, 0, 0) (16) the lcd drive method is set to the frame reversal drive. line reversal number register: (db4, db3, db2, db1, db0) = (1, 0, 0, 0, 0) on the other hand, when the reset command is used, only the conditions (8) to (15) above are set. as is shown in the ?mpu interface (example for reference)?, the res pin is connected to the reset pin of the mpu and the initialization of this lsi is made simultaneously with the resetting of the mpu. this lsi always has to be reset using the res pin at the time the power is switched on. also, excessive current can flow through this lsi when the control signal from the mpu is in the high impedance state. it is necessary to take measures to ensure that the input pins of this lsi do not go into the high impedance state after the power has been switched on. when the built-in lcd drive power supply circuit of the ML9059E is not used, it is necessary that res = ?l? when the external lcd drive power supply goes on. during the period when res = ?l?, although the oscillator circuit is operating, the display timing generator would have stopped and the pins cl, fr, frs, and dof would have been tied to the ?h? level. there is no effect on the pins db0 to db7. fedl9059e-01 lapis semiconductor ML9059E 54/72 examples of settings for the instructions when using the internal power supply immediately after power-on *(a): carry out power control set within 5ms after releasing the reset state. the 5ms duration changes depending on the panel characteristics and the value of the smoothing capacitor. we recommend verification of operation using an actual unit. *(b): when trace resistance in cog mounting does not exist, wait for over 300 ms. since this value varies with trace resistance, v1, smoothing capacitors, or voltage multiplier capacitors in cog mounting, confirm operation on an actual circuit board when using this lsi. notes: sections to be referred to *1: functional description ?reset circuit? *2: description of operation ?lcd bias set? *3: description of operation ?adc select? *4: description of operation ?common output state select? *5: description of operation ?line reversal/frame reversal drive select? *6: functional description ?power supply circuit?, operation description ?voltage v1 adjustment internal resistor ratio set? *7: functional description ?power supply circuit?, description of operation ?electronic potentiometer? *8: functional description ?power supply circuit?, description of operation ?power control set? v dd -v ss power supply on when the pin r es = ?l? power supply stabilization release reset state ( r es pin = ?h?) initial settings state (default) *1 wait for more than 300 ms function setting using command input (user settings) lcd bias set a dc select common output state select line reversal/frame reversal drive select *2 *3 *4 *5 function setting using command input (user settings) setting voltage v1 adjustment internal resistor ratio electronic potentiometer *6 *7 *8 *(a) function stabilization using command input (user settings) power control set initial setting state complete *(b) fedl9059e-01 lapis semiconductor ML9059E 55/72 when not using the internal power supply immediately after power-on *(a): enter the power save state within 5ms after releasing the reset state. *(b): carry out power control set within 5ms after releasing the power save state. the 5ms duration in *(a) and *(b) changes depending on the panel characteristics and the value of the smoothing capacitor. we recommend verification of operation using an actual unit. *(c): when trace resistance in cog mounting does not exist, wait for over 300 ms. since this value varies with trace resistance, v1, smoothing capacitors, or voltage multiplier capacitors in cog mounting, confirm operation on an actual circuit board when using this lsi. notes: sections to be referred to *1: functional description ?reset circuit? *2: description of operation ?lcd bias set? *3: description of operation ?adc select? *4: description of operation ?common output state select? *5: description of operation ?line reversal/frame reversal drive select? *6: functional description ?power supply circuit?, description of operation ?voltage v1 adjustment internal resistor ratio set? *7: functional description ?power supply circuit?, description of operation ?electronic potentiometer? *8: functional description ?power supply circuit?, description of operation ?power control set? *9: the power save state can be either the sleep state or the standby state. description of operation ?power save (compound command)? *( a) *( b) v dd -v ss power supply on when the pin r es = ?l? power supply stabilization release reset state ( r es pin = ?h?) initial settings state (default) *1 power save off function setting using command input (user settings) lcd bias set a dc select common output state select line reversal/frame reversal drive select *2 *3 *4 *5 function setting using command input (user settings) setting voltage v1 adjustment internal resistor ratio electronic potentiometer *6 *7 *8 function setting using command input (user settings) power control set wait for more than 300 ms start power save mode (compound command) *9 *9 initial setting state complete c) *( fedl9059e-01 lapis semiconductor ML9059E 56/72 data display notes: sections to be referred to *10: description of operation ?display start line set? *11: description of operation ?page address set? *12: description of operation ?column address set? *13: description of operation ?display data write? *14: description of operation ?display on/off? end of initial settin g s end of data display function stabilization using command input (user settings) display start line set *10 function stabilization using command input (user settings) dis p la y on/off *14 function stabilization using command input (user settings) display data write *13 function stabilization using command input (user settings) page address set *11 function stabilization using command input (user settings) column address se t *12 end of dis p la y data write? yes no end of p a g e write? yes no fedl9059e-01 lapis semiconductor ML9059E 57/72 power supply off (*15) any state function stabilization using command input (user settings) power save *16 v dd -v ss power supply off notes: sections to be referred to *15: the power supply of this lsi is switched off after switching off the internal power supply. function description ?power supply circuit? if the power supply of this lsi is switched off when the internal power supply is still on, since the state of supplying power to the built-in lcd drive circuits continues for a short duration, it may affect the display quality of the lcd panel. always follow the power supply switching off sequence. *16: description of operation ?power save? *17: after reset is input the power supply may off without obeying above sequence. refresh a lthough the ML9059E holds operation state by commands, excessive external noise might change the internal state. on a chip-mounting and system level, it is necessary to take countermeasures against preventing noise from occurring. it is recommended to use the refresh sequence periodically to control sudden noise. *18: regardless of presence of setting of ?read-modify-write?commanfd, please carry out ?end? command. set to the state in which all commands have been set. test mode release command (e3(h)) refresh ram - lcd bias set - adc select - display forwar/reverse - set ?lcd all-on display? on - common output state select - lcd drive mode set - static indecator register set - voltage v1 adjustment internal resistance ratio set - electronic potnetiometer - power control set - release the read-modify-write sate(end) (*18) - set ?nop? operation - display start line set - page address set - column address set - display data write - display on fedl9059e-01 lapis semiconductor ML9059E 58/72 mpu interface the ML9059E series ics can be connected directly to the 80-series and 68-series mpus. further, by using the serial interface, it is possible to operate the lsi with a minimum number of signal lines. in addition, it is possible to expand the display area by using the ML9059E series lsis in a multiple chip configuration. in this case, it is possible to select the individual lsi to be accessed using the chip select signals. ? 80-series mpu ?? 68-series mpu ?? serial interface v dd r eset v ss v cc gnd a0 a1 to a7 iorq db0 to db7 r d w r r es v dd v ss a0 c s1 cs2 db0 to db7 r d w r r es c86 p/ s decoder v dd r eset v ss v cc gnd a0 a1 to a15 vma db0 to db7 e r/ w r es v dd v ss a0 c s1 cs2 db0 to db7 e r/ w r es c86 p/ s decoder v dd r eset v ss v cc gnd port 5 port1 port2 r es v dd v ss a0 c s1 cs2 si scl r es c86 p/ s can be tied to either level. mpu ML9059E mpu ML9059E mpu ML9059E port 4 port 3 fedl9059e-01 lapis semiconductor ML9059E 59/72 pad configuration pad layout c hip size : 9.164 ? 2.982 mm pad coordinates pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 1 dummy -4462.5 -1376.0 21 cs1 -2762.5 -1376.0 2 dummy -4377.5 -1376.0 22 cs2 -2677.5 -1376.0 3 dummy -4292.5 -1376.0 23 v dd -2592.5 -1376.0 4 dummy-b -4207.5 -1376.0 24 res -2507.5 -1376.0 5 dummy-b -4122.5 -1376.0 25 a0 -2422.5 -1376.0 6 dummy-b -4037.5 -1376.0 26 v ss -2337.5 -1376.0 7 dummy-b -3952.5 -1376.0 27 wr -2252.5 -1376.0 8 dummy-b -3867.5 -1376.0 28 rd -2167.5 -1376.0 9 v ss -3782.5 -1376.0 29 v dd -2082.5 -1376.0 10 dummy-b -3697.5 -1376.0 30 db0 -1997.5 -1376.0 11 dummy-b -3612.5 -1376.0 31 db1 -1912.5 -1376.0 12 dummy-b -3527.5 -1376.0 32 db2 -1827.5 -1376.0 13 dummy-b -3442.5 -1376.0 33 db3 -1742.5 -1376.0 14 dummy-b -3357.5 -1376.0 34 db4 -1657.5 -1376.0 15 test1 -3272.5 -1376.0 35 db5 -1572.5 -1376.0 16 frs -3187.5 -1376.0 36 db6 -1487.5 -1376.0 17 fr -3102.5 -1376.0 37 db7 -1402.5 -1376.0 18 cl -3017.5 -1376.0 38 dummy-b -1317.5 -1376.0 19 dof -2932.5 -1376.0 39 v dd -1232.5 -1376.0 20 v ss -2847.5 -1376.0 40 v dd -1147.5 -1376.0 note: leave dummy and dummy-b pads open. do not run traces around. run traces through dummy and dummy-b pads individually, not in common. 104 105 148 149 308 309 347 1 fedl9059e-01 lapis semiconductor ML9059E 60/72 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 41 v dd -1062.5 -1376.0 81 v1 2337.5 -1376.0 42 v dd -977.5 -1376.0 82 v1 2422.5 -1376.0 43 v dd -892.5 -1376.0 83 v2 2507.5 -1376.0 44 v dd -807.5 -1376.0 84 v2 2592.5 -1376.0 45 v in -722.5 -1376.0 85 v3 2677.5 -1376.0 46 v in -637.5 -1376.0 86 v3 2762.5 -1376.0 47 v in -552.5 -1376.0 87 v4 2847.5 -1376.0 48 v in -467.5 -1376.0 88 v4 2932.5 -1376.0 49 v in -382.5 -1376.0 89 v5 3017.5 -1376.0 50 v ss -297.5 -1376.0 90 v5 3102.5 -1376.0 51 v ss -212.5 -1376.0 91 vr 3187.5 -1376.0 52 v ss -127.5 -1376.0 92 vr 3272.5 -1376.0 53 v ss -42.5 -1376.0 93 v dd 3357.5 -1376.0 54 v ss 42.5 -1376.0 94 m/ s 3442.5 -1376.0 55 v ss 127.5 -1376.0 95 cls 3527.5 -1376.0 56 v ss 212.5 -1376.0 96 v ss 3612.5 -1376.0 57 v out 297.5 -1376.0 97 c86 3697.5 -1376.0 58 v out 382.5 -1376.0 98 p/ s 3782.5 -1376.0 59 vc6+ 467.5 -1376.0 99 v dd 3867.5 -1376.0 60 vc6+ 552.5 -1376.0 100 dummy 3952.5 -1376.0 61 vc6+ 637.5 -1376.0 101 v ss 4037.5 -1376.0 62 vc4+ 722.5 -1376.0 102 irs 4122.5 -1376.0 63 vc4+ 807.5 -1376.0 103 v dd 4207.5 -1376.0 64 vc4+ 892.5 -1376.0 104 dummy 4292.5 -1376.0 65 vs2- 977.5 -1376.0 105 dummy 4443.0 -1049.9 66 vs2- 1062.5 -1376.0 106 dummy 4443.0 -997.9 67 vs2- 1147.5 -1376.0 107 dummy 4443.0 -945.9 68 vs1- 1232.5 -1376.0 108 dummy 4443.0 -893.9 69 vs1- 1317.5 -1376.0 109 dummy 4443.0 -841.9 70 vs1- 1402.5 -1376.0 110 dummy 4443.0 -789.9 71 vc5+ 1487.5 -1376.0 111 dummy 4443.0 -737.9 72 vc5+ 1572.5 -1376.0 112 dummy 4443.0 -685.9 73 vc5+ 1657.5 -1376.0 113 dummy 4443.0 -633.9 74 vc3+ 1742.5 -1376.0 114 dummy 4443.0 -581.9 75 vc3+ 1827.5 -1376.0 115 dummy 4443.0 -529.9 76 vc3+ 1912.5 -1376.0 116 dummy 4443.0 -477.9 77 v ss 1997.5 -1376.0 117 dummy 4443.0 -425.9 78 v rs 2082.5 -1376.0 118 dummy 4443.0 -373.9 79 v rs 2167.5 -1376.0 119 dummy 4443.0 -321.9 80 v dd 2252.5 -1376.0 120 dummy 4443.0 -269.9 fedl9059e-01 lapis semiconductor ML9059E 61/72 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 121 com23 4443.0 -217.9 161 dummy 3504.7 1352.5 122 com22 4443.0 -165.9 162 dummy 3452.7 1352.5 123 com21 4443.0 -113.9 163 dummy 3400.7 1352.5 124 com20 4443.0 -61.9 164 seg0 3348.7 1352.5 125 com19 4443.0 -9.9 165 seg1 3296.7 1352.5 126 com18 4443.0 42.1 166 seg2 3244.7 1352.5 127 com17 4443.0 94.1 167 seg3 3192.7 1352.5 128 com16 4443.0 146.1 168 seg4 3140.7 1352.5 129 com15 4443.0 198.1 169 seg5 3088.7 1352.5 130 com14 4443.0 250.1 170 seg6 3036.7 1352.5 131 com13 4443.0 302.1 171 seg7 2984.7 1352.5 132 com12 4443.0 354.1 172 seg8 2932.7 1352.5 133 com11 4443.0 406.1 173 seg9 2880.7 1352.5 134 com10 4443.0 458.1 174 seg10 2828.7 1352.5 135 com9 4443.0 510.1 175 seg11 2776.7 1352.5 136 com8 4443.0 562.1 176 seg12 2724.7 1352.5 137 com7 4443.0 614.1 177 seg13 2672.7 1352.5 138 com6 4443.0 666.1 178 seg14 2620.7 1352.5 139 com5 4443.0 718.1 179 seg15 2568.7 1352.5 140 com4 4443.0 770.1 180 seg16 2516.7 1352.5 141 com3 4443.0 822.1 181 seg17 2464.7 1352.5 142 com2 4443.0 874.1 182 seg18 2412.7 1352.5 143 com1 4443.0 926.1 183 seg19 2360.7 1352.5 144 com0 4443.0 978.1 184 seg20 2308.7 1352.5 145 coms1 4443.0 1030.1 185 seg21 2256.7 1352.5 146 dummy 4443.0 1082.1 186 seg22 2204.7 1352.5 147 dummy 4443.0 1134.1 187 seg23 2152.7 1352.5 148 dummy 4443.0 1186.1 188 seg24 2100.7 1352.5 149 dummy 4128.7 1352.5 189 seg25 2048.7 1352.5 150 dummy 4076.7 1352.5 190 seg26 1996.7 1352.5 151 dummy 4024.7 1352.5 191 seg27 1944.7 1352.5 152 dummy 3972.7 1352.5 192 seg28 1892.7 1352.5 153 dummy 3920.7 1352.5 193 seg29 1840.7 1352.5 154 dummy 3868.7 1352.5 194 seg30 1788.7 1352.5 155 dummy 3816.7 1352.5 195 seg31 1736.7 1352.5 156 dummy 3764.7 1352.5 196 seg32 1684.7 1352.5 157 dummy 3712.7 1352.5 197 seg33 1632.7 1352.5 158 dummy 3660.7 1352.5 198 seg34 1580.7 1352.5 159 dummy 3608.7 1352.5 199 seg35 1528.7 1352.5 160 dummy 3556.7 1352.5 200 seg36 1476.7 1352.5 fedl9059e-01 lapis semiconductor ML9059E 62/72 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 201 seg37 1424.7 1352.5 241 seg77 -655.3 1352.5 202 seg38 1372.7 1352.5 242 seg78 -707.3 1352.5 203 seg39 1320.7 1352.5 243 seg79 -759.3 1352.5 204 seg40 1268.7 1352.5 244 seg80 -811.3 1352.5 205 seg41 1216.7 1352.5 245 seg81 -863.3 1352.5 206 seg42 1164.7 1352.5 246 seg82 -915.3 1352.5 207 seg43 1112.7 1352.5 247 seg83 -967.3 1352.5 208 seg44 1060.7 1352.5 248 seg84 -1019.3 1352.5 209 seg45 1008.7 1352.5 249 seg85 -1071.3 1352.5 210 seg46 956.7 1352.5 250 seg86 -1123.3 1352.5 211 seg47 904.7 1352.5 251 seg87 -1175.3 1352.5 212 seg48 852.7 1352.5 252 seg88 -1227.3 1352.5 213 seg49 800.7 1352.5 253 seg89 -1279.3 1352.5 214 seg50 748.7 1352.5 254 seg90 -1331.3 1352.5 215 seg51 696.7 1352.5 255 seg91 -1383.3 1352.5 216 seg52 644.7 1352.5 256 seg92 -1435.3 1352.5 217 seg53 592.7 1352.5 257 seg93 -1487.3 1352.5 218 seg54 540.7 1352.5 258 seg94 -1539.3 1352.5 219 seg55 488.7 1352.5 259 seg95 -1591.3 1352.5 220 seg56 436.7 1352.5 260 seg96 -1643.3 1352.5 221 seg57 384.7 1352.5 261 seg97 -1695.3 1352.5 222 seg58 332.7 1352.5 262 seg98 -1747.3 1352.5 223 seg59 280.7 1352.5 263 seg99 -1799.3 1352.5 224 seg60 228.7 1352.5 264 seg100 -1851.3 1352.5 225 seg61 176.7 1352.5 265 seg101 -1903.3 1352.5 226 seg62 124.7 1352.5 266 seg102 -1955.3 1352.5 227 seg63 72.7 1352.5 267 seg103 -2007.3 1352.5 228 seg64 20.7 1352.5 268 seg104 -2059.3 1352.5 229 seg65 -31.3 1352.5 269 seg105 -2111.3 1352.5 230 seg66 -83.3 1352.5 270 seg106 -2163.3 1352.5 231 seg67 -135.3 1352.5 271 seg107 -2215.3 1352.5 232 seg68 -187.3 1352.5 272 seg108 -2267.3 1352.5 233 seg69 -239.3 1352.5 273 seg109 -2319.3 1352.5 234 seg70 -291.3 1352.5 274 seg110 -2371.3 1352.5 235 seg71 -343.3 1352.5 275 seg111 -2423.3 1352.5 236 seg72 -395.3 1352.5 276 seg112 -2475.3 1352.5 237 seg73 -447.3 1352.5 277 seg113 -2527.3 1352.5 238 seg74 -499.3 1352.5 278 seg114 -2579.3 1352.5 239 seg75 -551.3 1352.5 279 seg115 -2631.3 1352.5 240 seg76 -603.3 1352.5 280 seg116 -2683.3 1352.5 fedl9059e-01 lapis semiconductor ML9059E 63/72 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 281 seg117 -2735.3 1352.5 315 com27 -4443.0 874.1 282 seg118 -2787.3 1352.5 316 com28 -4443.0 822.1 283 seg119 -2839.3 1352.5 317 com29 -4443.0 770.1 284 seg120 -2891.3 1352.5 318 com30 -4443.0 718.1 285 seg121 -2943.3 1352.5 319 com31 -4443.0 666.1 286 seg122 -2995.3 1352.5 320 com32 -4443.0 614.1 287 seg123 -3047.3 1352.5 321 com33 -4443.0 562.1 288 seg124 -3099.3 1352.5 322 com34 -4443.0 510.1 289 seg125 -3151.3 1352.5 323 com35 -4443.0 458.1 290 seg126 -3203.3 1352.5 324 com36 -4443.0 406.1 291 seg127 -3255.3 1352.5 325 com37 -4443.0 354.1 292 seg128 -3307.3 1352.5 326 com38 -4443.0 302.1 293 seg129 -3359.3 1352.5 327 com39 -4443.0 250.1 294 seg130 -3411.3 1352.5 328 com40 -4443.0 198.1 295 seg131 -3463.3 1352.5 329 com41 -4443.0 146.1 296 dummy -3515.3 1352.5 330 com42 -4443.0 94.1 297 dummy -3567.3 1352.5 331 com43 -4443.0 42.1 298 dummy -3619.3 1352.5 332 com44 -4443.0 -9.9 299 dummy -3671.3 1352.5 333 com45 -4443.0 -61.9 300 dummy -3723.3 1352.5 334 com46 -4443.0 -113.9 301 dummy -3775.3 1352.5 335 com47 -4443.0 -165.9 302 dummy -3827.3 1352.5 336 coms0 -4443.0 -217.9 303 dummy -3879.3 1352.5 337 dummy -4443.0 -269.9 304 dummy -3931.3 1352.5 338 dummy -4443.0 -321.9 305 dummy -3983.3 1352.5 339 dummy -4443.0 -373.9 306 dummy -4035.3 1352.5 340 dummy -4443.0 -425.9 307 dummy -4087.3 1352.5 341 dummy -4443.0 -477.9 308 dummy -4139.3 1352.5 342 dummy -4443.0 -529.9 309 dummy -4443.0 1186.1 343 dummy -4443.0 -581.9 310 dummy -4443.0 1134.1 344 dummy -4443.0 -633.9 311 dummy -4443.0 1082.1 345 dummy -4443.0 -685.9 312 com24 -4443.0 1030.1 346 dummy -4443.0 -737.9 313 com25 -4443.0 978.1 347 dummy -4443.0 -789.9 314 com26 -4443.0 926.1 fedl9059e-01 lapis semiconductor ML9059E 64/72 ML9059E alignment mark specification 1 alignment mark coordinates alignment mark x(m) y(m) a ?4270.3 1364.5 b 4259.7 1364.5 c 4455 ?1180.9 d ?4455 ?1180.9 e ?4458.5 1368 f 4458.5 ?1368 alignment mark construction layer a , b, c, d: metal layer e,f:bump layer alignment mark specification symbol parameter mark size(m) a, b, c, d 34 a alignment mark width e, f 43 a, b, c, d 100 b alignment mark size e, f 98 a, b, c 60 alignment mark-to-adjacent pad metal distance (min.) d 106.6 e 109.4 c alignment mark-to-adjacent pad bump distance (min.) f 77 a b a b bump bump c c a b a b metal c c metal (0 a b c d x y (0,0) e f ? ? ? ? ? ? ? ? ? ????? ??????????????????? coordinate point coordinate point fedl9059e-01 lapis semiconductor ML9059E 65/72 ML9059E gold bump specification gold bump specification symbol parameter min. typ. max. unit a bump pitch (min.section:segment section) 52 ? ? ? m b bump size (segment section:pitch direction) 29 32 35 ? m c bump size (segment section:depth direction) 114 117 120 ? m d bumo-to-bump distance (segment section:pitch direction) 17 20 23 ? m e bump pitch (min.section:input section) 85 ? ? ? m f bump size (input section:pitch direction) 57 60 63 ? m g bump size (input section:depth direction) 67 70 73 ? m h bumo-to-bump distance (input section:pitch direction) 22 25 28 ? m i bump size (figure ?l? alignment mark: length) 95 98 101 ? m j bump size (figure ?l? alignment mark: width) 40 43 46 ? m ? pad center-to-bump center allowable error ? ? 2 ? m k bump height 12 15 18 ? m ? bumph height dispersion inside chip (range) ? ? 3 ? m l bump edge height ? ? 3 ? m ? shear strength (g) 18 ? ? g ? bump hardness: high (hv: 25g load) 50 ? 110 hv ? bump hardness: low (hv: 25g load) 30 ? 70 hv ? chip thickness: 625 ? 15 ? m ? chip size: 9.164mm ? 2.982mm top view and cross section view a b c d k l j i e h f segment section cross section view figure ?l? alignment mark in p ut section g fedl9059e-01 lapis semiconductor ML9059E 66/72 reference data open r v in v ss v out + v c6+ ? v c4+ v s2 ? ? v s1 ? v c5+ v c3+ + ? + ? vin=4.8v ? c1 i load c1 c1 r r r r r r r equivalent circuit to 3-time voltage multiplier with trace resistances external to cog-mounted chip 6 7 8 9 10 11 12 13 14 15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 r=0 ? r=100 ? r=200 ? voltage multiplier output voltage vout [v] ML9059E voltage multiplier load characteristics - load current de p endenc y at 3-time multi p lication evaluation conditions tj=90 ?c voltage multiplier capacitor c1=1 ? f vin=4.8v, 3-time multiplication only a voltage multiplier circuit operates by power control set command ?2c? load current iload [ma] ML9059E chip fedl9059e-01 lapis semiconductor ML9059E 67/72 reference data vin vss vc6+ vc4+ v s2 ? vs1 ? v c5+ v c3+ + ? + ? + ? v in=4.5v v out + ? i load c1 c1 c1 c1 r r r r r r r r r 7 8 9 10 11 12 13 14 15 16 17 18 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 r=0? r=100? r=200? ML9059E chip equivalent circuit to 4-time voltage multiplier with trace resistances external to cog-mounted chip ML9059E voltage multiplier load characteristics - load current dependency at 4-time multiplication voltage multiplier output voltage vout [v] evaluation conditions tj=90 ?c voltage multiplier capacitor c1=1 ? f vin=4.5v,4-time multiplication only a voltage multiplier circuit operates by power control set command ?2c? load current iload [ma] fedl9059e-01 lapis semiconductor ML9059E 68/72 equivalent circuit for evaluating power-up stabilization time in cog mounting open v in v ss v out + ? dumm y vc6+ v c4+ v s2 ? v s1 ? v c5+ v c3+ + ? + ? + ? v 1 v 2 v 3 v 4 v 5 + ? + ? + ? + ? 200 ? 200 ? v in=5.0 v c1 c1 c1 c1 r r r r r r r r c2 c 2 c2 c2 + ? v 1 v 2 v 3 v 4 v 5 + ? + ? + ? + ? v in v ss v out + ? dumm y vc6+ vc4+ v s2 ? v s1 ? v c5+ v c3+ + ? + ? + ? v in=4.5v 200 ? r r r r r r r r r c1 c1 c1 c1 c1 c2 c2 c2 c2 equivalent circuit to 3-time voltage multiplier with trace resistances external to cog-mounted chip equivalent circuit to 4-time voltage multiplier with trace resistances external to cog-mounted chip ML9059E chip ML9059E chip 200 ? 200 ? 200 ? 200 ? 200 ? 200 ? 200 ? fedl9059e-01 lapis semiconductor ML9059E 69/72 reference data (the rise time until v1-v5 is stabilized when command ?2f? is input after power-on in cog mounting.) 3-time voltage multiplication 0 50 100 150 200 250 300 00.511.522.533.544.55 c2=0.47 f c2=1.0 f 4-time voltage multiplication 0 50 100 150 200 250 300 00.511.522.533.544.55 c2=0.47 f c2=1.0 f reference value of v1-v5 rise stabilization time in ML9059E cog mounting conditions :vin=4.5v,4-time multiplication,v1=12v,trace resistance external to cog-mounted chip r=150 ? , t j =-40? c to +85 ? c parameter: smoothin g ca p acitor c2 rise time [ms] rise time [ms] parameter: smoothin g ca p acitor c2 reference value of v1-v5 rise stabilization time in ML9059E cog mounting conditions :vin=5v,3-time multiplication,v1=12v,trace resistance external to cog-mounted chip r=150 ? , tj=-40 ? c to +85 ? c value of voltage multiplier capacitor c1 [ ? f] value of voltage multiplier capacitor c1 [ ? f] fedl9059e-01 lapis semiconductor ML9059E 70/72 reference data (the rise time until v1-v5 is stabilized when command ?2f? is input after power-on in cog mounting.) 3-time voltage multiplication 0 50 100 150 200 250 300 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 r=100 ? r=200 ? 4-time voltage multiplication 0 50 100 150 200 250 300 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 r=100 r=200 parameter: trace resistance external to cog-mounted chi p rise time [ ms ] rise time [ms] v1 voltage [v] v1 voltage [v] rise time [ms] parameter: trace resistance external to cog-mounted chi p reference value of v1-v5 rise stabilization time in ML9059E cog mounting conditions :vin=5v, 3-time multiplication, tj=-40 ? c to +85 ? c volta g e multi p lier ca p acito r c1=3.3 ? f , smoothin g ca p acitor c2=1 ? f reference value of v1-v5 rise stabilization time in ML9059E cog mounting conditions :vin=4.5v, 4-time multiplication, tj=-40 ? c to +85 ? c volta g e multi p lier ca p acito r c1=3.3 ? f , smoothin g ca p acitor c2=1 ? f fedl9059e-01 lapis semiconductor ML9059E 71/72 revision history page document no. date previous edition current edition description fedl9059e-01 april. 13, 2007 ? ? final edition 1 fedl9059e-01 lapis semiconductor ML9059E 72/72 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the pr escribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a me dical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2007 - 2011 lapis semiconductor co., ltd . |
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